OpenTitan UART
==============

This site is a working example of :doc:`sphinx-svdomain <usage>` applied to a
real SystemVerilog design. It combines source-driven API documentation from the
`OpenTitan UART RTL`_ with explanatory pages based on the `UART hardware IP
specification`_.

The UART is a full-duplex serial peripheral with an 8-bit data word, optional
even or odd parity, one stop bit, programmable baud rate, receive and transmit
FIFOs, loopback modes, and interrupt reporting. This example focuses on how
those concepts map onto discoverable SystemVerilog objects rather than
duplicating the complete upstream specification.

The RTL logic is pinned to OpenTitan commit
``377160a7ea64bf6b187127db5f2bc6819b7ff196``. Declaration-facing comments in
the local copy use the doc-comment syntax consumed by autodoc, making the
generated API both descriptive and reproducible.

.. toctree::
   :maxdepth: 2
   :caption: UART documentation

   architecture
   serial-protocol
   rtl-api
   usage

.. _OpenTitan UART RTL: https://github.com/lowRISC/opentitan/tree/377160a7ea64bf6b187127db5f2bc6819b7ff196/hw/ip/uart/rtl
.. _UART hardware IP specification: https://opentitan.org/book/hw/ip/uart/index.html