RTL API reference
=================

Every object below is extracted from the vendored SystemVerilog at build time.
The package is emitted first so its types and parameters can be linked from
later module signatures.

Register package
----------------

.. sv:autopackage:: uart_reg_pkg
   :source: ../rtl/uart_reg_pkg.sv

Integration wrapper
-------------------

.. sv:automodule:: uart
   :source: ../rtl/uart.sv

UART core
---------

.. sv:automodule:: uart_core
   :source: ../rtl/uart_core.sv

Transmit datapath
-----------------

.. sv:automodule:: uart_tx
   :source: ../rtl/uart_tx.sv

Receive datapath
----------------

.. sv:automodule:: uart_rx
   :source: ../rtl/uart_rx.sv

Generated register block
------------------------

.. sv:automodule:: uart_reg_top
   :source: ../rtl/uart_reg_top.sv