Serial protocol
===============

The line is high while idle. A frame starts with a low start bit, carries eight
data bits least-significant bit first, optionally carries a parity bit, and ends
with a high stop bit. The diagram below uses ``sphinxcontrib-wavedrom`` and is
rendered as a self-contained SVG during the Sphinx build.

.. wavedrom::
   :caption: UART frames without and with parity
   :align: center

   {
     "signal": [
       {"name": "baud", "wave": "p..........."},
       {"name": "8N1 tx", "wave": "10333333331.",
        "data": ["D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7"]},
       {},
       {"name": "baud", "wave": "p............"},
       {"name": "8P1 tx", "wave": "103333333341.",
        "data": ["D0", "D1", "D2", "D3", "D4", "D5", "D6", "D7", "P"]}
     ],
     "head": {"text": "UART serial frame, LSB first"},
     "config": {"skin": "hardmatrix"}
   }

Transmit path
-------------

:sv:mod:`uart_tx` loads a frame when :sv:port:`uart_tx.wr` is asserted. The
start bit, :sv:port:`uart_tx.wr_data`, optional
:sv:port:`uart_tx.wr_parity`, and stop bit are placed in an eleven-bit shift
register. :sv:port:`uart_tx.tick_baud_x16` is divided by 16; each resulting baud
tick shifts the next bit onto :sv:port:`uart_tx.tx`.

Receive path
------------

:sv:mod:`uart_rx` also consumes :sv:port:`uart_rx.tick_baud_x16`. A falling
edge on :sv:port:`uart_rx.rx` starts reception, but the input is checked again
half a bit later so that a short glitch is rejected. Subsequent samples are
taken at bit centers. The block checks the stop bit and, when enabled, parity
before :sv:port:`uart_rx.rx_valid` marks the completed character.

See the upstream `serial-interface description`_ for the protocol-level
specification and its receiver sampling analysis.

.. _serial-interface description: https://opentitan.org/book/hw/ip/uart/doc/theory_of_operation.html#serial-interface-both-directions