Architecture

The uart wrapper connects the UART to TileLink, alert, RACL, chip-I/O, and interrupt interfaces. Register accesses are decoded by uart_reg_top; the resulting uart_reg_pkg::uart_reg2hw_t and uart_reg_pkg::uart_hw2reg_t structures connect the register block to uart_core.

The core separates the two serial directions into uart_tx and uart_rx.

RTL responsibilities

Object	Responsibility	Selected API
uart	Integration wrapper	uart.tl_i, uart.cio_rx_i, uart.cio_tx_o, and the interrupt outputs
uart_reg_top	Generated bus-facing register block	uart_reg_top.reg2hw and uart_reg_top.hw2reg
uart_core	FIFOs, baud generation, loopback, status, and interrupts	uart_core.rx, uart_core.tx, and the two register structures
uart_tx	Parallel-to-serial datapath	uart_tx.wr_data, uart_tx.wr, and uart_tx.tx
uart_rx	Oversampled serial-to-parallel datapath	uart_rx.rx, uart_rx.rx_data, and uart_rx.rx_valid

FIFO sizing

The package constants uart_reg_pkg::RxFifoDepth and uart_reg_pkg::TxFifoDepth configure 64 receive entries and 32 transmit entries respectively. uart_core uses those values to size the FIFO depth counters and instantiate the two synchronous FIFOs.

Data flow

On transmit, software writes a byte through the register block. The core queues it, then presents it on uart_tx.wr_data while pulsing uart_tx.wr. The transmitter shifts the frame out through uart_tx.tx.

On receive, uart_core synchronizes and optionally majority-filters the external input before forwarding it to uart_rx.rx. A valid frame produces uart_rx.rx_data and uart_rx.rx_valid; the core accepts the byte only when neither uart_rx.frame_err nor uart_rx.rx_parity_err is asserted.

The upstream theory of operation covers register programming, loopback, interrupt behavior, break detection, and baud-rate calculations in detail.