Serial protocol

The line is high while idle. A frame starts with a low start bit, carries eight data bits least-significant bit first, optionally carries a parity bit, and ends with a high stop bit. The diagram below uses sphinxcontrib-wavedrom and is rendered as a self-contained SVG during the Sphinx build.

UART frames without and with parity

Transmit path

uart_tx loads a frame when uart_tx.wr is asserted. The start bit, uart_tx.wr_data, optional uart_tx.wr_parity, and stop bit are placed in an eleven-bit shift register. uart_tx.tick_baud_x16 is divided by 16; each resulting baud tick shifts the next bit onto uart_tx.tx.

Receive path

uart_rx also consumes uart_rx.tick_baud_x16. A falling edge on uart_rx.rx starts reception, but the input is checked again half a bit later so that a short glitch is rejected. Subsequent samples are taken at bit centers. The block checks the stop bit and, when enabled, parity before uart_rx.rx_valid marks the completed character.

See the upstream serial-interface description for the protocol-level specification and its receiver sampling analysis.